A SRAM Memory Cell Design in FPGA

Design of Low Power Sram Memory Using 8t Sram Cell

Low power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. As modern technology is spreading fast, it is very important to design low power, high performance, and fast responding SRAM (Static Random Access Memory) since they are critical component in high performance processors. The Conventional 6T SRAM cell is very muc...

An Efficient LUT Design on FPGA for Memory-Based Multiplication

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...

FPGA Implementation of SRAM Memory Testing Technique Using BISR Scheme

As RAM is major component in present day SOC, by Improving the yield of RAM improves the yield of SOC. So the repairable memories play a vital role in improving the yield of chip .Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). If each repairable RAM uses one self contained BISR circuit (Dedicated BISR scheme), then the area cost of B...

FPGA based Ternary Content Addressable Memory using SRAM

Ternary content addressable memory, TCAM is a semiconductor memory device, operates for determining a match between received search data and stored data in TCAM bitcells. TCAM performs high speed lookup operations, but when compared to RAM technology the conventional TCAM circuitry suffers from certain limitations such as low access time, low storage capacity, circuit complexity and much high c...

Sram System Design for Memory Based Computing